Semiconductor device and method for manufacturing the same

ABSTRACT

A semiconductor device which has a low-profile laminate structure including an interlayer insulating film and includes an easily formed alignment mark, and a method for manufacturing the semiconductor device. The semiconductor device includes a photoelectric transducer formed in a semiconductor substrate, a stopper film in a mark area, a first interlayer insulating film formed over the stopper film and photoelectric transducer, a first metal interconnect, and a second interlayer insulating film. A through hole which penetrates the first and second interlayer insulating films and reaches the stopper film is made and a first concave is made in the upper surface of a conductive layer in the through hole. A second concave to serve as an alignment mark is made in a second metal interconnect above the first concave.

CROSS-REFERENCE TO RELATED APPLICATIONS

The disclosure of Japanese Patent Application No. 2010-106317 filed onMay 6, 2010 including the specification, drawings and abstract isincorporated herein by reference in its entirety.

BACKGROUND

The present invention relates to a semiconductor device and a method formanufacturing the same and more particularly to a semiconductor deviceincluding a photoelectric transducer such as a photodiode and a methodfor manufacturing the same.

For image sensors used in digital cameras, particularly single-lensreflex digital cameras, improvement in the sensitivity to external lightis desirable. For example, when a photodiode is used in an image sensor,the top of the photodiode is usually covered by a laminate structure inwhich thin films including interlayer insulating films are stacked.

In making this laminate structure, a thin film formed at a later step ispatterned as desired using a previously formed layer as a mark foralignment. Here, the mark for alignment is, for example, a concave madein a portion of a metal layer. For example, Japanese Unexamined PatentPublication No. Hei 3 (1991)-138920 discloses a semiconductor device inwhich such an alignment mark is made.

SUMMARY

In order for an image sensor to increase its sensitivity to externallight which it receives, it is desirable to decrease the thickness(height) of the laminate structure lying over, for example, a photodiodeas a constituent of the image sensor. By decreasing the thickness of theinterlayer insulating film as a constituent of the laminate structure,the possibility that the intensity of light entering the photodiode fromoutside decreases due to the interlayer insulating film can be reduced.

However, when the height of the laminate structure is decreased, thedepth of a concave made in the upper surface of the metal film filled ina hole penetrating the laminate structure is also decreased. Therefore,if the height of the laminate structure is decreased, it will bedifficult to make a clear alignment mark in the hole as a concave in asufficiently thick metal film. If the alignment mark concave is not deepenough and not clear, there will be difficulty in alignment at theexposure step of the later photoengraving process.

On the other hand, if the height of the laminate structure is increased,it will be easy to make a concave which is deep enough and sufficientlyclear but the intensity of light entering the photodiode from outsidewill decrease. This may result in deterioration in the sensitivity toexternal light entering the photodiode.

In the semiconductor device described in Japanese Unexamined PatentPublication No. Hei 3 (1991)-138920, the hole for an alignment markreaches the surface of the semiconductor substrate. Thus the alignmentmark hole is deep and the thickness of the metal interconnect film onthe sidewall of the alignment mark hole largely varies in the radialdirection of the hole. This causes deterioration in alignment accuracy.

The present invention has been made in view of the above problem and anobject thereof is to provide a semiconductor device which has alow-profile or thin laminate structure including an interlayerinsulating film and ensures high alignment accuracy, and a method formanufacturing the same.

According to one aspect of the present invention, a semiconductor deviceis configured as follows. The semiconductor device includes: asemiconductor substrate having a main surface; a photoelectrictransducer formed in the semiconductor substrate; a stopper film formedover the main surface of the semiconductor substrate; a first interlayerinsulating film formed over the stopper film and over the photoelectrictransducer; a first metal interconnect formed over the first interlayerinsulating film; and a second interlayer insulating film formed so as tocover the first metal interconnect and the photoelectric transducer. Ahole which penetrates the first and second interlayer insulating filmsand reaches the stopper film is made. The device further includes anin-hole conductive layer formed along a sidewall and a bottom wall ofthe hole with a first concave in an upper surface thereof and a secondmetal interconnect formed over the in-hole conductive layer and thesecond interlayer insulating film, in which a second concave to serve asan alignment mark is located just above the first concave and in anupper surface thereof.

According to a second aspect of the present invention, a method formanufacturing a semiconductor device includes the following steps.First, a photoelectric transducer is formed in a semiconductor substratehaving a main surface. A metal interconnect is formed over the mainsurface of the semiconductor substrate. An interlayer insulating film isformed over the metal interconnect and over the photoelectrictransducer. A hole reaching the metal interconnect is made in theinterlayer insulating film. A conductive layer for filling the hole isformed. The upper surface of the conductive layer is selectively removedto make the upper surface of the conductive layer recessed from an uppersurface of the interlayer insulating film. A metal layer is formed overthe upper surface of the conductive layer and over the upper surface ofthe interlayer insulating film so as to make a concave to serve as analignment mark, in the upper surface of the metal layer just above theconductive layer.

According to the first aspect of the invention, the depth of the hole inwhich an alignment mark is formed is equivalent to the sum of thethickness of the first interlayer insulating film and that of the secondinterlayer insulating film. A sufficiently deep concave is made in theupper surface of the in-hole conductive layer formed along the sidewalland bottom wall of this deep hole. Therefore, the semiconductor devicecan have a clear alignment mark with a sufficient depth which is formedabove the concave.

In the manufacturing method according to the second aspect of theinvention, the upper surface of the conductive layer filling the hole isrecessed from the upper surface of the interlayer insulating film. Aconcave to serve as an alignment mark is made above the recessed uppersurface of the conductive layer. As a consequence, a clear alignmentmark with a sufficient depth is formed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic plan view showing a semiconductor device accordingto a first embodiment of the present invention in an on-wafer state;

FIG. 2 is a schematic plan view showing the area encircled by dottedline II in FIG. 1 in enlarged form;

FIG. 3 is a schematic plan view showing a chip corresponding to the areaencircled by dotted line III in FIG. 2 in enlarged form;

FIG. 4 is a schematic plan view showing an example of an alignment markin the first embodiment;

FIG. 5 is a schematic sectional view taken along the line V-V in FIG. 4;

FIG. 6 is a schematic plan view showing another example of an alignmentmark in the first embodiment which is different from the one shown inFIG. 4;

FIG. 7 is a schematic sectional view taken along the line VII-VII inFIG. 6;

FIG. 8 is a schematic plan view showing another example of an alignmentmark in the first embodiment which is different from the ones shown inFIGS. 4 and 6;

FIG. 9 is a schematic sectional view taken along the line IX-IX in FIG.8;

FIG. 10 is a schematic sectional view showing the structure of thesemiconductor device according to the first embodiment;

FIG. 11 is a schematic sectional view showing the first step of themethod for manufacturing the semiconductor device according to the firstembodiment;

FIG. 12 is a schematic sectional view showing the second step of themethod for manufacturing the semiconductor device according to the firstembodiment;

FIG. 13 is a schematic sectional view showing the third step of themethod for manufacturing the semiconductor device according to the firstembodiment;

FIG. 14 is a schematic sectional view showing the fourth step of themethod for manufacturing the semiconductor device according to the firstembodiment;

FIG. 15 is a schematic sectional view showing the fifth step of themethod for manufacturing the semiconductor device according to the firstembodiment;

FIG. 16 is a schematic sectional view showing the sixth step of themethod for manufacturing the semiconductor device according to the firstembodiment;

FIG. 17 is a schematic sectional view showing the seventh step of themethod for manufacturing the semiconductor device according to the firstembodiment;

FIG. 18 is a schematic sectional view showing the eighth step of themethod for manufacturing the semiconductor device according to the firstembodiment;

FIG. 19 is a schematic sectional view showing the ninth step of themethod for manufacturing the semiconductor device according to the firstembodiment;

FIG. 20 is a schematic sectional view showing the tenth step of themethod for manufacturing the semiconductor device according to the firstembodiment;

FIG. 21 is a schematic sectional view showing the eleventh step of themethod for manufacturing the semiconductor device according to the firstembodiment;

FIG. 22 is a schematic sectional view showing the twelfth step of themethod for manufacturing the semiconductor device according to the firstembodiment;

FIG. 23 is a schematic sectional view showing the thirteenth step of themethod for manufacturing the semiconductor device according to the firstembodiment;

FIG. 24 is a schematic sectional view showing the fourteenth step of themethod for manufacturing the semiconductor device according to the firstembodiment;

FIG. 25A is a schematic sectional view showing a conductive layer formedin the mark area in the first embodiment and FIG. 2B is a schematicsectional view showing a conductive layer as a comparative example forthe first embodiment;

FIG. 26 is a photo showing the cross section of a mark suitable for useas an alignment mark together with item numbers corresponding to thedimensional data shown in Table 1;

FIG. 27 is a photo showing the cross section of a mark unsuitable foruse as an alignment mark together with item numbers corresponding to thedimensional data shown in Table 1;

FIG. 28 is a schematic sectional view showing a variation of thesemiconductor device according to the first embodiment in which thestopper film is different from the one shown in FIG. 10;

FIG. 29 is a schematic sectional view showing a variation of thesemiconductor device according to the first embodiment in which theconductive layer is different from the one shown in FIG. 28;

FIG. 30 is a schematic sectional view showing a variation of thesemiconductor device according to the first embodiment in which thestopper film is different from the ones shown in FIGS. 10 and 28;

FIG. 31 is a schematic sectional view showing a variation of thesemiconductor device according to the first embodiment in which theconductive layer is different from the one shown in FIG. 30;

FIG. 32 is a schematic sectional view showing a step subsequent to thestep shown in FIG. 18 in the first embodiment in the method formanufacturing a semiconductor device according to a second embodiment ofthe present invention;

FIG. 33 is a schematic sectional view showing a step subsequent to thestep shown in FIG. 32 in the method for manufacturing a semiconductordevice according to the second embodiment;

FIG. 34 is a schematic sectional view showing a step subsequent to thestep shown in FIG. 33 in the method for manufacturing a semiconductordevice according to the second embodiment;

FIG. 35 is a schematic sectional view showing a step subsequent to thestep shown in FIG. 34 in the method for manufacturing a semiconductordevice according to the second embodiment; and

FIG. 36 is a schematic sectional view showing a step subsequent to thestep shown in FIG. 35 in the method for manufacturing a semiconductordevice according to the second embodiment.

DETAILED DESCRIPTION

Next, the preferred embodiments of the present invention will bedescribed referring to the accompanying drawings.

First Embodiment

First, a semiconductor device according to the first embodiment in anon-wafer state is described below.

Referring to FIG. 1, a plurality of chip regions IMC for image sensorsare formed on a semiconductor wafer SW. The chip regions IMC each have arectangular planar shape and are arranged in a matrix pattern.

Referring to FIG. 2, each of the chip regions IMC has a region PDR forthe formation of a photoelectric transducer such as a photodiode and aregion PCR for the formation of a peripheral circuit for controlling thephotodiode. The formation region PCR is provided on both sides of theformation region PDR. A dicing line region DLR is formed between chipregions IMC. Alignment marks are arranged in the dicing line region DLR.

The semiconductor wafer SW is divided into plural semiconductor chips bydicing the semiconductor wafer SW along the dicing line region DLR.

Next, the semiconductor device according to the first embodiment in theform of a chip will be described. Referring to FIG. 3, a semiconductorchip SC has a rectangular planar shape and includes a photodiodeformation region PDR, peripheral circuit formation regions PCR, and adicing line region DLR. Among the alignment marks in the dicing lineregion DLR, some are cut by dicing and the others remain uncut.

An example of the alignment marks is shown in FIGS. 4 and 5, in whicheach alignment mark is long with a length between 30 μm and 34 μm in aplan view and a width between 4 μm and 8 μm and the spacing betweenneighboring alignment marks is 16 μm. Another example is shown in FIGS.6 and 7, in which each alignment mark is long with a length of 36 μm ina plan view and a width of 2 μm and the spacing between neighboringalignment marks is 14 μm. A further example is shown in FIGS. 8 and 9,in which each alignment mark is 4 μm square in a plan view and thespacing between neighboring alignment marks is 16 μm. In some cases,recesses or concaves in the upper surface of a film are used as suchalignment marks.

Next, an image sensor both in an on-wafer state and in the form of achip and its alignment mark will be described.

Referring to FIG. 10, the image sensor in this embodiment has aphotodiode PTO in a photodiode area and a control transistor CTR in aperipheral circuit area. A concave MK as an alignment mark is formed ina mark area.

More specifically, the image sensor is formed in an n-region NTR of asilicon semiconductor substrate SUB. The photodiode area, peripheralcircuit area and alignment mark area are separated from each other by afield oxide film FO formed over the surface of the semiconductorsubstrate SUB.

The photodiode PTO includes a p-type well region PWR1 and an n-typeimpurity region NPR. The p-type well region PWR1 is formed in thephotodiode area in the surface of the semiconductor substrate SUB. Then-type impurity region NPR is formed in the p-type well region PWR1 inthe surface of the semiconductor substrate SUB and makes a p-n junctionwith the p-type well region PWR1.

The photodiode area also includes a MIS (Metal Insulator Semiconductor)transistor such as a switching transistor SWTR. Particularly theswitching transistor SWTR includes a pair of source/drain regions NPRand NR/NDR, a gate insulating film GI, and a gate electrode GE. The pairof n-type source/drain regions NPR and NR/NDR are spaced and arranged inthe p-type well region PWR1 in the surface of the semiconductorsubstrate SUB. NPR as one of the pair of n-type source/drain regions NPRand NR/NDR is integral with the n-type impurity region NPR of thephotodiode PTO and electrically coupled with it. NR/NDR as the other ofthe pair of source/drain regions NPR and NR/NDR includes an n+ impurityregion NDR as a high concentration region and an n-type impurity regionNR as an LDD (Lightly-Doped Drain). The gate electrode GE is formed overthe surface of the semiconductor substrate SUB between the pair ofsource/drain regions NPR and NR/NDR through the gate insulating film GI.

In addition, a p+ impurity region PDR for coupling with an overlyinginterconnect is formed in the surface of the semiconductor substrate SUBin the p-type well region PWR1.

A laminated anti-reflection coating including a silicon oxide film OFand a silicon nitride film NF is formed over the surface of thesemiconductor substrate SUB in a way to cover the photodiode PTO. Oneend of this anti-reflection coating OF/NF lies over one sidewall of thegate electrode GE. A sidewall insulating layer including a silicon oxidefilm OF and a silicon nitride film NF as a residue of theanti-reflection coating OF/NF is formed on the other sidewall of thegate electrode GE.

For example, a p-type well region PWR2 is formed in the surface of thesemiconductor substrate SUB in the peripheral circuit area. A controlelement for controlling the operation of plural photodiodes PTO isformed in this p-type well region PWR2 and the control element includes,for example, a MIS transistor CTR.

The MIS transistor CTR includes a pair of n-type source/drain regionsNR/NDR, a gate insulating film GI, and a gate electrode GE. The pair ofn-type source/drain regions NR/NDR are spaced and formed in the surfaceof the semiconductor substrate SUB. The pair of n-type source/drainregions NR/NDR each include an n-type impurity region NDR as a highconcentration region and an n-type impurity region NR as an LDD.

The gate electrode GE is formed over the surface of the semiconductorsubstrate SUB between the pair of n-type source/drain regions NR/NDRthrough a gate insulating film GI. A sidewall insulating layer includingan oxide film OF and a nitride film NF as an anti-reflection coatingresidue is formed on the sidewall of the gate electrode GE.

The material of the gate electrode GE of each MIS transistor in thephotodiode area and peripheral circuit area may be impurity-dopedpolycrystal silicon or a metal such as TiN.

In the photodiode area, peripheral circuit area, and alignment mark area(dicing line region), an interlayer insulating film II1 is formed overthe surface of the semiconductor substrate SUB in a way to cover theabove elements (photodiode PTO, MIS transistors SWTR and CTR). In thephotodiode area and peripheral circuit area, a patterned first metalinterconnect AL1 is formed over the interlayer insulating film II1. Thisfirst metal interconnect AL1 is electrically coupled, for example, withthe p+ impurity region PDR or n+ impurity region NDR through a contactC1 filling a contact hole of the interlayer insulating film II1.

In the alignment mark area, a stopper film AL1 is formed over theinterlayer insulating film II1. For example, this stopper film AL1 isformed by separating the same metal film as used for the metalinterconnect AL1 using ordinary photoengraving and etching techniquesand may be made of aluminum (Al) or copper (Cu).

An interlayer insulating film II2 is formed over the interlayerinsulating film II1 in a way to cover the metal interconnect AL1 andstopper film AL1. In the photodiode area and peripheral circuit area, apatterned second metal interconnect AL2 is formed over the interlayerinsulating film II2. This second metal interconnect AL2 is electricallycoupled with the first metal interconnect AL1 through a conductive layerT1 filling a through hole of the interlayer insulating film II2.

An interlayer insulating film II3 is formed over the interlayerinsulating film II2 in a way to cover the metal interconnect AL2. In thephotodiode area and peripheral circuit area, a patterned third metalinterconnect AL3 is formed over the interlayer insulating film II3. Thisthird metal interconnect AL3 is electrically coupled with the secondmetal interconnect AL2 through a conductive layer T2 filling a throughhole of the interlayer insulating film II3.

In the alignment mark area, a through hole DTH is made in the interlayerinsulating films II2 and II3, penetrating the interlayer insulatingfilms II2 and II3 and reaching the stopper film AL1. A conductive layer(in-hole conductive layer) DT is formed in the through hole DTH alongthe sidewall and bottom wall of the through hole DTH. This conductivelayer DT is, for example, made of tungsten (W). A concave (firstconcave) CAV is made in the upper surface of the conductive layer DT.

A metal film for an alignment mark (second metal interconnect) AL3 isformed over the upper surface of the conductive layer DT and over theupper surface of the interlayer insulating film II3. A concave (secondconcave) MK to serve as an alignment mark is made in the upper surfaceof the alignment mark metal film AL3 and just above the concave CAV ofthe conductive layer DT. For example, this alignment mark metal film AL3is formed from the same metal film as used for the metal interconnectsAL3 in the photodiode and peripheral circuit areas using ordinaryphotoengraving and etching techniques and may be made of aluminum orcopper.

An interlayer insulating film 114 is formed over the interlayerinsulating film II3 in a way to cover the metal interconnects AL3 in thephotodiode and peripheral circuit areas and alignment mark metal filmAL3. A passivation film PASF is formed over the interlayer insulatingfilm 114. A condenser lens LENS is placed over the passivation film PASFand just above the photodiode PTO. This condenser lens LENS is used tocollect light and throw the light on the photodiode PTO.

The interlayer insulating films II1, II2, II3, and II4 are, for example,made of silicon oxide or a material which is different from the metalstopper film AL1 in terms of etching selectivity (for example, etchingselectivity in etching the interlayer insulating film II2 or II3 for theformation of the through hole DTH).

The sidewall of the through hole DTH forms a continuous surface in thedirection from the upper surface of the interlayer insulating film II3to the stopper film AL1 without any level difference in the boundarybetween the interlayer insulating films II2 and II3. In other words, inthe cross section shown in FIG. 10, the sidewall of the through hole DTHextends linearly from the upper surface of the interlayer insulatingfilm II3 to the surface of the stopper film AL1. A barrier metal filmmay be formed on the sidewall and bottom wall of the through hole DTH,though not shown.

The concave MK shown in the sectional view of FIG. 10 is tapereddownward (triangular). However, if the width (horizontal dimension inFIG. 10) of the concave CAV is increased, the lower width will be almostequal to the upper width as shown in FIGS. 5, 7, and 9.

FIG. 10 shows one photodiode PTO and one switching element SWTR in thephotodiode area, one control transistor CTR in the peripheral circuitarea, and one concave MK in the mark area. Actually, however, more thanone photodiode PTO and more than one switching element SWTR are spacedand arranged in each of the individual chips as shown in FIG. 3.

Next, the method for manufacturing the semiconductor device according tothe first embodiment as shown in FIG. 10 will be explained referring toFIGS. 11 to 23.

Referring to FIG. 11, a semiconductor substrate SUB, made of asemiconductor material (silicon, germanium, etc) which depends on thewavelength of light in use, is prepared. An n-region NTR as an n−epitaxial growth layer is formed in the surface of the semiconductorsubstrate SUB. Then, p-type well regions PWR1 and PWR2 are formed in thephotodiode area and peripheral circuit area respectively. Field oxidefilms FO are formed in the boundary between the photodiode andperipheral circuit areas and the boundary between the peripheral circuitand mark areas. The field oxide films FO electrically isolate theformation regions of the photodiode, peripheral circuit and mark areasfrom each other.

Then, a gate insulating film GI and a gate electrode GE are formed indesired places. The concrete procedure is as follows. Agate insulatingfilm is formed over the main surface of the semiconductor substrate SUB,for example, by thermal oxidation. A polycrystal silicon film or thelike to form a gate electrode is deposited over the gate insulatingfilm.

Then, the gate insulating film and polycrystal silicon or the like arepatterned so that a gate insulating film GI and a gate electrode GE areformed as shown in FIG. 11.

Referring to FIG. 12, an n-type impurity region NPR is formed inside thep-type well region PWR1 of the photodiode area using ordinaryphotoengraving and ion implantation techniques. A photodiode PTO,including the p-type well region PWR1 and n-type impurity region NPR, isthus formed.

Referring to FIG. 13, an n-type region NR to become an LDD is formed inthe surface of the semiconductor substrate SUB inside each of the p-typewell regions PWR1 and PWR2 of the photodiode area using ordinaryphotoengraving and ion implantation techniques.

Referring to FIG. 14, for example, a silicon oxide film OF and a siliconnitride film NF are deposited one upon the other in order all over thesurface of the semiconductor substrate SUB. Then, the silicon oxide filmOF and silicon nitride film NF are patterned in a way to cover at leastthe photodiode PTO using ordinary photoengraving and etching techniquesso that an anti-reflection coating including the silicon oxide film OFand silicon nitride film NF is made.

Also, by etching the silicon oxide film OF and silicon nitride film NF,a sidewall insulating layer as a residue of the anti-reflection coatingis formed on the sidewall of each gate electrode GE.

Referring to FIG. 15, a p+ region PDR is formed in a prescribed place ofthe p-type well region PWR1 using ordinary photoengraving and ionimplantation techniques.

Referring to FIG. 16, an n-type region NDR is formed in a prescribedplace of each of the photodiode and peripheral circuit areas usingordinary photoengraving and ion implantation techniques. The n-typeregion NDR is an n+ region which has a higher impurity concentrationthan the n-type region NR.

Referring to FIG. 17, an interlayer insulating film II1 as a siliconoxide film is formed by CVD (Chemical Vapor Deposition). Then theinterlayer insulating film II1 is polished by CMP (Chemical MechanicalPolishing) so that its upper surface is flattened. Furthermore, contactholes CH1 are made in the interlayer insulating film II1 using ordinaryphotoengraving and etching techniques in a way to reach the n-typeregion NDR and p-type region PDR.

Referring to FIG. 18, a conductive film C1, for example, made oftungsten is filled in each contact hole CH1. For example, CVD isemployed for this process and a thin tungsten film is also formed overthe interlayer insulating film II1. The thin tungsten film over theinterlayer insulating film II1 is removed by CMP. Then, a thin film, forexample, made of aluminum is formed over the interlayer insulating filmII1, for example, by sputtering. Then, using ordinary photoengraving andetching techniques, a metal interconnect AL1, for example, made ofaluminum is formed in each of the photodiode and peripheral circuitareas and a stopper film AL1, for example, made of aluminum is formed inthe mark area.

The metal interconnects AL1 in the photodiode and peripheral circuitareas are electrically coupled to the n-type regions NDR and p-typeregion PDR through the contacts C1.

Referring to FIG. 19, an interlayer insulating film II2 is formed overthe interlayer insulating film II1, metal interconnects AL1 and stopperfilm AL1 and through holes TH1 are made in desired places (above themetal interconnects AL1). The interlayer insulating film II2 and throughholes TH1 are formed with the same procedure as the interlayerinsulating film II1 and contact holes CH1. Since the etching selectivityof the interlayer insulating film II2 is different from that of themetal interconnects AL1, downward etching of the interlayer insulatingfilm II2 can be easily ended at a point where the metal interconnect AL1is reached.

Referring to FIG. 20, a conductive layer T1, for example, made oftungsten is filled in each through hole TH1. Then, a pattern of metalinterconnects AL2, for example, made of aluminum is made over theinterlayer insulating film II2. The conductive layer T1 and metalinterconnects AL2 are formed with the same procedure as the contacts C1and metal interconnects AL1. No metal interconnects AL2 are formed inthe mark area.

Referring to FIG. 21, an interlayer insulating film II3 is formed overthe interlayer insulating film II2 and metal interconnects AL2 andthrough holes TH2 are made in desired places (above the metalinterconnects AL2). The interlayer insulating film II3 and through holesTH2 are formed with the same procedure as the interlayer insulating filmII2 and through holes TH1.

The through holes TH2 are formed in the photodiode and peripheralcircuit areas in a way to reach the metal interconnects AL2 from the topof the interlayer insulating film II3. On the other hand, in the markarea the through hole DTH is formed in a way to reach the stopper filmAL1 from the top of the interlayer insulating film II3. The through holeDTH is made by etching the interlayer insulating films II2 and II3 in away to penetrate them. Since the etching selectivity of the interlayerinsulating films II2 and II3 is different from that of the stopper filmAL1, etching for the formation of the through hole DTH can be easilyended at a point where the stopper film AL1 is reached.

Referring to FIG. 22, a conductive film DL, for example, made oftungsten is formed over the interlayer insulating film II3 in a way tofill the through holes TH2 and through hole DTH. The diameter and depthof the through hole DTH are larger than the diameter and depth of thethrough holes TH2. Therefore, while the conductive film DL completelyfills the through holes TH2, it does not fill the through hole DTHcompletely and stretches along the sidewall and bottom wall of thethrough hole DTH. After that, the conductive film DL is polished andremoved by CMP until the upper surface of the interlayer insulating filmII3 is exposed.

Referring to FIG. 23, as a result of the above CMP process, a conductivelayer T2 is formed from the conductive film DL in the through holes TH2and a conductive layer DT is formed from the conductive film DL in thethrough hole DTH. The conductive layer DT is formed along the sidewalland bottom wall of the through hole DTH with a concave CAV in its uppersurface.

In the above film formation process, some portion of the conductive filmDT filled in the through hole DTH does not reach the uppermost surfaceof the interlayer insulating film II3 in a plan view and that portion isshallower than the other surrounding portion. As a consequence, theconcave CAV (first concave) is formed.

A metal film AL3 is formed in a way to cover the upper surfaces of theconductive layer DT, conductive layers T2, and interlayer insulatingfilm II3. A concave (second concave) MK is made in the upper surface ofthe metal film AL3 just above the concave CAV. This concave MK is usedas an alignment mark in positioning a photo mask (reticle) in thephotoengraving process for patterning the metal film AL3.

Specifically, in the process of patterning the metal film AL3,photoresist (photoreceptor) is first coated on the metal film AL3. Then,after positioning the photo mask using the concave MK as an alignmentmark, a prescribed portion of the photoresist is exposed to lighttransmitted through the photo mask. After that, the photoresist isdeveloped and patterned into a prescribed shape. Using the patternedphotoresist as a mask, the metal film AL3 is patterned into a prescribedshape by etching. Then, the photoresist is removed by asking or asimilar technique.

As a result of patterning the metal film AL3, metal interconnects AL3are formed from the metal film AL3 in the photodiode and peripheralcircuit areas and the metal film AL3 for an alignment mark with theconcave MK remains over the conductive layer DT in the mark area.

Referring to FIG. 24, an interlayer insulating film 114 is formed overthe interlayer insulating film II3 in a way to cover the metalinterconnects AL3 and the alignment mark metal film AL3. The uppersurface of the interlayer insulating film 114 is flattened, for example,by CMP. After that, a silicon nitride film is deposited over theinterlayer insulating film 114, for example, by CVD. This siliconnitride film becomes a passivation film PASF.

Lastly, a condenser lens LENS is placed just above the photodiode PTOand the image sensor as shown in FIG. 10 is thus completed.

Next, the effect of this embodiment will be described referring to FIGS.25A and 25B. FIG. 25A shows the structure of the mark area in thisembodiment shown in FIG. 10. The through hole DTH penetrates theinterlayer insulating films II2 and II3. FIG. 25B shows a comparativeexample in which a through hole STH penetrates only the interlayerinsulating film II3. Since the comparative example shown in FIG. 25B isstructurally the same as the first embodiment shown in FIG. 25A exceptthat the through hole STH penetrates only the interlayer insulating filmII3, the same elements are designated by the same reference numerals andtheir descriptions are omitted here.

A shallow hole like the through hole STH of the comparative exampleshown in FIG. 25B can be easily filled by the conductive layer DT. Thismeans that a concave CAV is hardly produced in the upper surface of theconductive layer DT which fills the through hole STH. If there is noconcave CAV in the upper surface of the conductive layer DT or theconcave is small, a concave to serve as an alignment mark is notproduced in the upper surface of the metal layer AL3 formed over theconductive layer DT. Also, even if a concave for an alignment mark isproduced, it will be very small and not suitable for use as an alignmentmark.

On the other hand, in the first embodiment shown in FIG. 25A, thethrough hole DTH is deeper, penetrating the two interlayer insulatingfilms II2 and II3. Therefore, it is not easy to fill the through holeDTH completely by the conductive layer DT, making it more likely toproduce a large (deep) concave CAV in the upper surface of theconductive layer DT. Thus, a large concave MK is easily produced in theupper surface of the metal film AL3 formed over the conductive layer DT.The large concave MK will serve as an alignment mark which ensures highalignment accuracy.

In this embodiment, since the depth of the through hole DTH correspondsto the combined thickness of the two interlayer insulating films, adeeper concave MK can be made than in the comparative example.Therefore, the intensity of light entering the photodiode PTO can beincreased by decreasing the thicknesses of the interlayer insulatingfilms II2 and II3 while keeping the required depth of the concave MK foruse as an alignment mark.

If a clear, deep concave MK is made, it will be easier to performpatterning using the concave MK as an alignment mark at a later step.This is explained below referring to FIGS. 26 and 27 and the tablebelow.

TABLE 1 Suitable as an Unsuitable as an alignment mark alignment mark(1) Mark depth 125 nm  12 nm (2) Mark-to-barrier 297 nm 365 nm metaldistance (3) Barrier metal  93 nm  80 nm thickness (4) Through hole 515nm 457 nm conductive layer thickness

The area encircled by dotted line in FIGS. 26 and 27 shows a concave MK.The dimensions represented by numbers 1 to 4 in FIGS. 26 and 27correspond to the dimensional data for items (1) to (4) of Table 1respectively. Dimensions related to a mark suitable for use as analignment mark (FIG. 26) are shown in the “Suitable as an alignmentmark” column of Table 1 and dimensions related to a mark unsuitable foruse as an alignment mark (FIG. 27) are shown in the “Unsuitable as analignment mark” column of Table 1.

The comparison shows that the mark suitable for use as an alignment markis larger in depth and also larger in the overall thickness (4) of theconductive layer in the through hole than the mark unsuitable for use asan alignment mark.

Since all the films are not flattened by CMP, the sum of numerical datafor items (1), (2) and (3) of Table 1 is not always equal to thenumerical data for item (4).

Furthermore, in this embodiment, since the through hole DTH does notreach the surface of the semiconductor substrate SUB, variation in theradial thickness of the concave MK is small. Therefore, alignmentaccuracy is improved.

Furthermore, in this embodiment, the wall surface of the through holeDTH is a continuous surface extending from the upper surface of theinterlayer insulating film II3 to the metal interconnect AL1 without anylevel difference in the boundary between the interlayer insulating filmsII2 and II3. This eliminates the possibility of variation in the radialthickness of the concave MK due to a level difference, ensuring highalignment accuracy.

In the formation of the through hole DTH in the mark area as mentionedabove, the stopper film AL1 is the first metal interconnect AL1.However, it is acceptable that the stopper film in the formation of thethrough hole DTH is the same silicon nitride film. NF as used for theanti-reflection coating in the photodiode PTO as shown in FIG. 28. Thisis because the silicon nitride film, the upper film of theanti-reflection coating, has a high etching selectivity with respect toan interlayer insulating film (silicon oxide film, etc).

The image sensor shown in FIG. 28 is different from the image sensorshown in FIG. 10 in terms of the stopper film in the mark area and thelayer in which the mark is made. In the structure shown in FIG. 28, thestopper film in the mark area is the silicon nitride film NF of theanti-reflection coating as mentioned above. The layer in which theconcave MK is made is the metal film AL2 formed separately using thesecond metal interconnect AL2. Since the image sensor shown in FIG. 28is almost the same as the image sensor shown in FIG. 10 except theabovementioned, the same elements in FIG. 28 as those in FIG. 10 aredesignated by the same reference numerals and their descriptions areomitted here.

The stopper film in the image sensor shown in FIG. 28 is formedseparately using the silicon nitride film NF of the photodiode PTO.Therefore, the stopper film is located under the interlayer insulatingfilm II1, so the level of the top of the through hole DTH is almostequal to the level of the top of the interlayer insulating film II2.However, it is also acceptable that as shown in FIG. 29, the level ofthe top of the through hole TTH is almost equal to the level of the topof the interlayer insulating film II3 like the structure shown in FIG.10. In that case, the through hole TTH penetrates three layers, namelyinterlayer insulating films II1, II2, and II3.

As another example, it is acceptable that as shown in FIG. 30, thestopper film is a thin film of polycrystal silicon which is the samematerial as that of the gate electrodes GE of the control transistor CTRand switching element SWTR. This is because polycrystal silicon has ahigh etching selectivity with respect to an interlayer insulating film(silicon oxide film, etc). The image sensor shown in FIG. 30 is almostthe same as the image sensor shown in FIG. 10 except theabove-mentioned.

The stopper film G1 in the image sensor shown in FIG. 30 is separatelyformed using the same layer as used for the gate electrodes GE of thecontrol transistor CTR and switching element SWTR. Therefore, thestopper film is located under the interlayer insulating film II1, so thelevel of the top of the through hole DTH is almost equal to the level ofthe top of the interlayer insulating film II2. However, it is alsoacceptable that as shown in FIG. 31, the level of the top of the throughhole TTH is almost equal to the level of the top of the interlayerinsulating film II3 like the structure shown in FIG. 10. In that case,the through hole TTH penetrates three layers, namely interlayerinsulating films II1, II2, and II3.

Second Embodiment

The second embodiment is different from the first embodiment in themethod for making a concave MK. Next, the method for manufacturing asemiconductor device (image sensor) according to the second embodimentwill be described referring to FIGS. 32 to 36.

In the second embodiment, the same steps as those shown in FIGS. 11 to18 in the first embodiment are taken. Specifically, a photodiode PTO isformed inside the semiconductor substrate SUB and metal interconnectsAL1 and a stopper film AL1 are formed over the main surface of thesemiconductor substrate SUB.

The step shown in FIG. 32 is different from the step shown in FIG. 19 inthe first embodiment in that a through hole STH is made in the mark areatoo. In other words, the through hole STH which penetrates theinterlayer insulating film II2 is made with the metal film AL1 in themark area as the stopper film.

Referring to FIG. 33, a conductive film Wa, for example, made oftungsten is formed over the interlayer insulating film II2 in a way tofill the through holes TH1 and through hole STH. The conductive film Wais formed, for example, by CVD. After that, the conductive film Wa ispolished and removed by CMP until the upper surface of the interlayerinsulating film II3 is exposed.

Referring to FIG. 34, as a result of the above CMP process, theconductive film Wa made of tungsten in the through holes TH1 and STHremains unremoved and becomes a conductive layer Wb. The upper surfaceof the conductive layer Wb which fills the through holes TH1 and STH isalmost flattened.

Referring to FIG. 35, some portions of the upper surface of the tungstenconductive layer Wb in the through holes TH1 and STH are selectivelyremoved by an etch-back technique. In this process, the upper surface ofthe tungsten conductive layer Wb is recessed downward with respect tothe upper surface of the interlayer insulating film II2, therebyproducing a concave CAV in the upper surface of the tungsten conductivelayer Wb.

Referring to FIG. 36, a thin metal filmAL2 a (metal layer), for example,made of aluminum is formed over the interlayer insulating film II2 andtungsten conductive layer Wb, for example, by sputtering. At this time,a concave MK to serve as an alignment mark is made in the upper surfaceof the thin metal film AL2 a just above the concave CAV of theconductive layer Wb in the through hole STH. Subsequently the thin metalfilm AL2 a is patterned using ordinary photoengraving and etchingtechniques to form metal interconnects, though not shown.

In pattering the thin metal film AL2 a, positioning (alignment) of thephoto mask is performed using the concaves MK made in the thin metalfilm AL2 a as alignment marks. Patterning of the thin metal film AL2 ais performed almost in the same way as pattering of the metal film AL3in the first embodiment.

After that, an interlayer insulating film II3 and so on are formed as inthe first embodiment and finally the image sensor is completed.

As shown in FIGS. 32 to 36, the image sensor in the second embodiment isalmost the same as the image sensor in the first embodiment except theabovementioned, so in FIGS. 32 to 36, the same elements as those in thefirst embodiment are designated by the same reference numerals and theirdescriptions are omitted here.

Next the effect of the second embodiment will be described.

If a conductive layer Wb is formed in the through hole STH made in thesingle interlayer insulating film II2 as mentioned above and theconductive layer DT (Wb) in the mark area is thin, a concave CAV may notbe produced in the upper surface of the conductive layer Wb. This isbecause a shallow hole like the through hole STH of the comparativeexample shown in FIG. 25B can be easily filled by the conductive layerDT.

In this embodiment, the upper surface of the conductive layer Wb isselectively removed by an etch-back technique as shown in FIGS. 34 and35. Consequently, the upper surface of the conductive layer Wb isrecessed with respect to the upper surface of the interlayer insulatingfilm II2, thereby producing a concave CAV in the upper surface of theconductive layer Wb. The concave CAV for an alignment mark is thus madein the upper surface of the conductive layer Wb in the through hole STH,which suggests that it is possible to make a sufficiently deep concaveCAV for an alignment mark in the upper surface of the conductive layerWb in the through hole STH made in the single interlayer insulating filmII2. Therefore, it is possible to improve the photosensitivity of thephotodiode PTO by decreasing the thickness of the interlayer insulatingfilm over the photodiode PTO and ensure high alignment accuracy.

FIGS. 32 to 36 show a case that the conductive layer DT (Wb) in thethrough hole STH is etched back. However, for example, even when theconductive layers in the contact holes and through holes made in theinterlayer insulating films II1 and II3 are similarly etched back, asimilar effect can be achieved. Furthermore, the conductive layer DT orTT shown in FIG. 29 or 31 may be etched back similarly. Furthermore, thestopper film for the conductive layer DT (TT) in the mark area is notlimited to a metal interconnect made of aluminum but it may be a siliconnitride film NF formed separately using the same layer as used for theanti-reflection coating shown in FIGS. 28 and 29 or a thin film formedseparately using the same layer as used for the gate electrodes shown inFIGS. 30 and 31.

In addition, in this embodiment, it is desirable to use an ordinary CVDtechnique (vapor growth method without sputtering during deposition) toform the conductive film Wa which fills the through hole STH. In somecases, a film which fills a hole in this way is formed by the vaporgrowth method called HDP (High Density Plasma)-CVD in which depositionand sputtering are performed simultaneously by applying a bias RF (RadioFrequency) to the wafer. In this method, the sidewall of the concave MKin the upper surface of the conductive film Wa hardly becomesperpendicular to the main surface of the semiconductor substrate SUB.Specifically, the sidewall of the concave MK becomes gradually narrowerin the depth direction from the upper surface of the conductive film Waand becomes triangular in a sectional view. As a result, the profile ofthe concave MK is unclear, so the concave MK as an alignment mark cannotensure high alignment accuracy.

On the other hand, when the through hole STH is filled by the conductivefilm Wa by the vapor growth method without sputtering during deposition,the sidewall of the concave MK in the upper surface of the conductivefilm Wa can be made perpendicular to the main surface of thesemiconductor substrate SUB. As a result, the profile of the concave MKis clear, so the concave MK as an alignment mark can ensure highalignment accuracy.

The second embodiment of the invention is different from the firstembodiment only in the abovementioned points. In other words, the secondembodiment is the same as the first embodiment in all other points suchas structure, conditions, procedure and effect.

It should be considered that the embodiments disclosed herein areillustrative in all aspects and not restrictive. The scope of thepresent invention is defined by the appended claims rather than by thedescription preceding them, and all changes that fall within metes andbounds of the claims, or equivalence of such metes and bounds aretherefore intended to be embraced by the claims.

The present invention can be used effectively for a semiconductor devicehaving a photoelectric transducer and a method for manufacturing thesame.

1. A semiconductor device comprising: a semiconductor substrate having amain surface; a photoelectric transducer formed in the semiconductorsubstrate; a stopper film formed over the main surface of thesemiconductor substrate; a first interlayer insulating film formed overthe stopper film and over the photoelectric transducer; a first metalinterconnect formed over the first interlayer insulating film; a secondinterlayer insulating film formed so as to cover the first metalinterconnect and the photoelectric transducer, with a hole made in thefirst and second interlayer insulating films, penetrating the first andsecond interlayer insulating films and reaching the stopper film; anin-hole conductive layer formed along a sidewall and a bottom wall ofthe hole with a first concave in an upper surface thereof; and a secondmetal interconnect formed over the in-hole conductive layer and thesecond interlayer insulating film, with a second concave to serve as analignment mark, located just above the first concave and in an uppersurface thereof.
 2. The semiconductor device according to claim 1,wherein the sidewall of the hole forms a continuous surface in adirection from an upper surface of the second interlayer insulating filmto the stopper film without any level difference in a boundary betweenthe first interlayer insulating film and the second interlayerinsulating film.
 3. The semiconductor device according to claim 1 or 2,wherein the stopper film is made of a material which is different inetching selectivity from the first and second interlayer insulatingfilms.
 4. The semiconductor device according to any of claims 1 to 3,wherein the stopper film is a third metal interconnect formed in a layerunder the first metal interconnect.
 5. The semiconductor deviceaccording to any of claims 1 to 3, wherein the stopper film is a filmformed separately using the same layer as used for an anti-reflectioncoating of the photoelectric transducer.
 6. The semiconductor deviceaccording to any of claims 1 to 3, wherein the stopper film is formedseparately using the same layer as used for a transistor gate electrode.7. A method for manufacturing a semiconductor device comprising thesteps of: forming a photoelectric transducer in a semiconductorsubstrate having a main surface; forming a metal interconnect over themain surface of the semiconductor substrate; forming an interlayerinsulating film over the metal interconnect and over the photoelectrictransducer; making, in the interlayer insulating film, a hole reachingthe metal interconnect; forming a conductive layer for filling the hole;removing an upper surface of the conductive layer selectively to makethe upper surface of the conductive layer recessed from an upper surfaceof the interlayer insulating film; and forming a metal layer over theupper surface of the conductive layer and over the upper surface of theinterlayer insulating film so as to make a concave to serve as analignment mark, in an upper surface of the metal layer just above theconductive layer.
 8. The method for manufacturing a semiconductor deviceaccording to claim 7, wherein the step of forming a conductive layer forfilling the hole includes: a step of forming the conductive layer so asto fill the hole and cover the interlayer insulating film; and a step ofpolishing and removing the conductive layer by a chemical mechanicalpolishing method until the upper surface of the interlayer insulatingfilm is exposed.
 9. The method for manufacturing a semiconductor deviceaccording to claim 8, wherein the conductive layer is formed by a vaporgrowth method without sputtering during formation of the film.